5.2-GHz CMOS HIPERLAN Transceivers

This paper describes the design of a CMOS frequency synthesizer targeting wireless local area network applications in the 5-GHz range, with emphasis on the HIPERLAN standard. Based on an integer-N architecture, the synthesizer produces a 5.2-GHz output as well as the quadrature phases of a 2.6-GHz carrier. Fabricated in a 0.4m digital CMOS technology, the circuit provides a channel spacing of 23 MHz at 5.2 GHz while exhibiting a phase noise of 115 dBc/Hz at 2.6 GHz and 100 dBc/Hz at 5.2 GHz at 10-MHz offset. The reference sidebands are at 50 dBc at 2.6 GHz and the power dissipation from a 2.6-V supply is 47 mW.